PURPOSE: To attain high speed data transfer for a position across the boundary of addresses by writing the first half of data at a write cycle, reading subsequent data at a read cycle and at the same time writing the latter part of preceding data.

CONSTITUTION: CPU 1 reads initial data R1 from a first memory 2, and data R 1 is bit-shifted in a shifter 5 and is written in an address (n) in a second memory 3 as data W11. Then, CPU 1 reads subsequent data R2, and an address selection circuit 9 gives address information n+1 of an address bus 16 to the second memory 3 by a control signal 18 from a control part 6. Then, the remaining part of data R1 is written in lower three bits of an address (n+1) as data W12. The operation is repeated and reading from the first memory 2 and writing into the second memory 3 are simultaneously executed. Thus, data is transferred at high speed without complicating circuit constitution even in the case of bit block transfer across the boundary of the addresses.