PURPOSE: To control the rise/fall timing, etc., of a system clock signal with a reset signal, to facilitate the matching of the circuit with a test device and shorten a test time, and to simplify the hardware and software of the test device, etc.

CONSTITUTION: This circuit is provided with a frequency-divided set pulse generating circuit 4 and a frequency division output control circuit 5 which generate a set pulse S and a reset pulse R in test mode according to the external reset signal RS. Frequency dividing circuits 2 and 3 are circuits whose output levels are controlled with the set pulse S and reset pulse R.