PURPOSE: To provide a system which controls a communication between the computer processor and plural peripheral devices which are operably connected to plural external buses.

CONSTITUTION: The computer processor, 14 is operably connected to a buffer transceiver circuit 81 like an internal bus 80 which is connected to the buffer transceiver circuit 81 through a local bus 110 is connected to buffers 21, 29, and 37. The buffer 21 is connected to an S bus 118, the buffer 29 is connected to a DRAM controller, and the buffer 37 is connected to an X bus. An internal peripheral device 140 is also connected operably to the internal bus 80. Bus control 90 is operably connected to the bus 80. High-speed characteristics of one peripheral device 132 and one memory device 124 may be actualized with a maximum potential without any limitation of a characteristic speed shown by the capacitance of the S bus 118. A combination of route specifications for operable interconnection that operation performed by the system 10 requires is predetermined and stored in a memory 91.