PURPOSE: To reduce remarkably a peak shift generated at reproduction of a recording pattern by the constitution that a recording timing correcting amount is to be changed in response to the recording pattern.

CONSTITUTION: A shift register 10 inputting a recording timing clock 1 of a code word and a bit serial input data 2 of the code word, and a DA71 inputting each output signal and transmitting a bit serial signal data 3 of the code word whose timing corrected in response to the output signal are provided. The shift register 10 transfers sequentially the data 2 into shift registers in the timing of the clock 1, and a timing correction circuit 15 sets respectively the delay time of delay circuits 21W24 as T21WT24, maximum delay time T21 and minimum delay time T24, i.e., delay times of T21>T22>T23>T24. When the data is a pattern of 00001001, a data 3 is outputted in the slowest timing D2 and when the data is a pattern of 10010000, the data 3 is outputted in the fastest timing (E2).