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Title:
SYSTEM FOR FUNCTION GENERATION
Document Type and Number:
Japanese Patent JPS58151680
Kind Code:
A
Abstract:

PURPOSE: To output accurately an optional function without requiring the temperature compensation, by using a binary code, which an input signal is converted to by an A/D converter, as an address of an ROM to read out a binary code corresponding to the input analog signal stored in the ROM preliminarily.

CONSTITUTION: An analog input signal 1 is converted to a digital binary code by an A/D converter 2, and a binary code output 3 of the converter 2 is inputted as an address of an ROM4. A binary code corresponding to the input signal 1 is stored preliminarily in the address corresponding to the binary code output 3 in the ROM4. The binary code stored in the ROM4 is read out by the output 3 of the binary code, and a converted binary code output 5 is converted to an analog signal by a D/A converter 6 and is outputted as an analog output signal 7. In such a constitution, an optional function is outputted accurately without providing the temperature compensation.


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Inventors:
SUZUKI EIJI
Application Number:
JP3335182A
Publication Date:
September 08, 1983
Filing Date:
March 03, 1982
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06G7/26; (IPC1-7): G06G7/26
Domestic Patent References:
JPS5729953B21982-06-25
JPS5325332A1978-03-09
Attorney, Agent or Firm:
Koshiro Matsuoka