To easily enable a synthesized logic circuit to correspond to original HDL and to easily recognize/correct a synthesized result by displaying intermediate signals, that respective pieces of parts information of HDL have in the logic circuit when parts information from parts information of the logic circuit, which are described by hardware description language HDL, are outputted as the logic circuit which is optimized by logically synthesizing them.

A compiling part 4 reads HDL 1 and generates an inner data base with boundary information 2 on an intermediate signal in HDL 1. An optimization part 5 optimizes the initial logic circuit of an AND/OR level in the inner data base with boundary information 2, while boundary information is held. A technology mapping part 6 holds the initial logic circuit as boundary information and allocates it to a function block within a semiconductor library 3. A timing optimizing part 7 optimizes delays with respect to the logic circuit 10 of a technology level in the inner data base with boundary information 2, in a state where boundary information is held.