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Patent Searching and Data


Title:
SYSTEM FOR PREVENTING WRITING MALFUNCTION
Document Type and Number:
Japanese Patent JPH02247804
Kind Code:
A
Abstract:

PURPOSE: To prevent the writing malfunction at the time of the interruption of a power source by providing a writing malfunction preventing circuit in parallel between a driving circuit and a head driving control circuit.

CONSTITUTION: The writing malfunction preventing circuit 3 does not operate as the transistor Tr 1 thereof is off in the normal time when the power source of the device is not interrupted. A writing action is executed without a response delay by the input of a writing control signal -WS to the head driving control circuit when this writing control signal is outputted from the driving circuit 1. The transistor Tr 1 turns on and the writing malfunction preventing circuit 3 operates to pass a current via a capacitor C 1 and the Tr 1 to the driving circuit 1 when the power source of the device is interrupted; therefore, the operation of a head driving controller 2 is prevented. The writing by the malfunction of the driving circuit at the time of the interruption of the power source is, therefore, surely prevented.


Inventors:
TANAKA HIROYUKI
UNO KOJI
Application Number:
JP6783189A
Publication Date:
October 03, 1990
Filing Date:
March 20, 1989
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G11B5/09; (IPC1-7): G11B5/09
Attorney, Agent or Firm:
Teiichi Ijiba (2 outside)