Title:
SYSTEM REST INTERLOCKING CIRCUIT
Document Type and Number:
Japanese Patent JPH0944201
Kind Code:
A
Abstract:
To reset a system without manually turning off once the power source of the system and then turning on the power source again.
This circuit consists principally of a CPU 1 as a control means which controls the whole system, a reset circuit 2 which resets the system, a timer 3 which controls the operation time of the reset circuit 2, an AND gate 4, and an inverting gate 6, and a reset signal output means which outputs a reset signal is provided in the CPU 1.
Inventors:
SATO KAZUO
Application Number:
JP19835795A
Publication Date:
February 14, 1997
Filing Date:
August 03, 1995
Export Citation:
Assignee:
YASKAWA ELECTRIC CORP
International Classes:
H01H9/54; G05B9/02; G05B19/05; (IPC1-7): G05B9/02; G05B19/05; H01H9/54
Attorney, Agent or Firm:
Wakabayashi Tadashi
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