Title:
SYSTEM SELECTING HIGH-RELIABILITY INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS57203976
Kind Code:
A
Abstract:
The selecting system makes use of a bank of amplifiers for successively and sequentially exciting P different types of integrated circuits assembled together in groups. The amplifying channels are periodically enabled one after the other by means of a demultiplexing circuit controlled from a processing and programming unit designated as PPU. The direct-current supplies comprise a programmable supply which is also addressed by the PPU and the output of which is applied to a switching matrix, the matrix being also addressed by the PPU and connected via P outputs respectively to the P groups of integrated circuits. Transmission of the excitation signals to the group of integrated circuits relating to said signals is performed by means of a second switching matrix addressed by the PPU. A mass memory unit such as a microprocessor is associated with the PPU and can have an electric functional test program for programming the excitation signals desired for selection.
Inventors:
SUTEFUAN SHIYAROO
Application Number:
JP8031582A
Publication Date:
December 14, 1982
Filing Date:
May 14, 1982
Export Citation:
Assignee:
THOMSON CSF
International Classes:
G06F11/24; G01R31/26; (IPC1-7): G01R31/26
Domestic Patent References:
| JPS53124984A | 1978-10-31 |