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Title:
TEMPORARY BONDING LAYER FOR SEMICONDUCTOR DEVICE MANUFACTURING, LAMINATE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2014212292
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a temporary bonding layer for semiconductor device manufacturing, laminate and a semiconductor device manufacturing method which can temporarily support a to-be-processed member (semiconductor wafer and the like) successfully and easily when mechanical or chemical treatment is performed on the to-be-processed member; and which can easily release a temporary support of a processed member without causing damage on the processed member even after being subjected to a process at a high temperature.SOLUTION: In a temporary bonding layer for semiconductor device manufacturing used for manufacturing of a semiconductor device having (A) a peeling layer and (B) an adhesive layer, which includes a process of performing heat treatment, the peeling layer is a layer having a softening point of 170°C and over, and the adhesive layer is a layer in which two and more types of regions having different adhesive forces from each other are provided on a surface by exposing the surface of the layer where adhesiveness increases or decreases depending on irradiation of active rays or radial rays.

Inventors:
KOYAMA ICHIRO
IWAI HISASHI
FUJIMAKI KAZUHIRO
Application Number:
JP2013137805A
Publication Date:
November 13, 2014
Filing Date:
July 01, 2013
Export Citation:
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Assignee:
FUJIFILM CORP
International Classes:
H01L21/304; B32B7/06; C09J4/00; C09J7/20; C09J201/00
Domestic Patent References:
JP2012124467A2012-06-28
JP4474854B22010-06-09
JP2012158715A2012-08-23
JPH01301739A1989-12-05
Attorney, Agent or Firm:
Patent business corporation patent firm Sykes