Title:
人工ニューラルネットワーク内のアナログニューラルメモリのための試験回路及び方法
Document Type and Number:
Japanese Patent JP7359935
Kind Code:
B2
Abstract:
Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. In one example, a method comprises programming a plurality of analog neural non-volatile memory cells in an array of analog neural non-volatile memory cells to store one of N different values, where N is a number of different levels that can be stored in any of the analog neural non-volatile memory cells; measuring a current drawn by the plurality of analog neural non-volatile memory cells; comparing the measured current to a target value; and identifying the plurality of the analog neural non-volatile memory cells as bad if the difference between the measured value and the target value exceeds a threshold.
Inventors:
Trang, Hugh, Van
Boo, Sun
Trin, Stefan
Hong, Stanley
Li, Ann
Remke, Stephen
Nguyen, Nya
Tiwari, bipin
Doe, Nan
Boo, Sun
Trin, Stefan
Hong, Stanley
Li, Ann
Remke, Stephen
Nguyen, Nya
Tiwari, bipin
Doe, Nan
Application Number:
JP2022503818A
Publication Date:
October 11, 2023
Filing Date:
December 21, 2019
Export Citation:
Assignee:
SILICON STORAGE TECHNOLOGY, INC.
International Classes:
G06G7/60; G06N3/063; G11C16/04; G11C16/34; G11C29/50
Domestic Patent References:
| JP2015506528A |
Foreign References:
| US20060098505 | ||||
| US9070481 | ||||
| WO2019135839A1 |
Attorney, Agent or Firm:
Patent Attorney Corporation Wisdom International Patent and Trademark Office