PURPOSE: To check with high quality by storing revisably information designating a function circuit to which a pseudo error signal is to be supplied and information designating the period of the signal is supplied to control the pseudo error signal to be supplied to each function circuit.
CONSTITUTION: An output of a decoder 3 is inputted to AND gates G1WGn based on information data in a register 2 by a test start signal, and a timing pulse ERP from an error generating time control circuit 7 based on the information data in registers 4, 5 is inputted to the AND gates G1WGn. When, e.g., the AND gate G1 is brought into the permissible state through the status combination of the decode output and the timing pulse ERP from the decoder 3, the pseudo error signal from a pseudo error signal generating circuit EG1 is supplied to the function circuit in a computer 10 via the AND gate G1 and when the result of operating processing is based on the error processing function, the circuit is discriminated as normal.
MARUO AKIHIRO
KAWANISHI KIYOSHI
| JPS5580158A | 1980-06-17 | |||
| JPS58107969A | 1983-06-27 |