Title:
TEST SYSTEM, AND IMPOSING METHOD FOR TEST SYSTEM
Document Type and Number:
Japanese Patent JP2004053392
Kind Code:
A
Abstract:
To allow imposition in response to a silicon cycle while restraining the influence of the silicon cycle.
The present invention provides an improved system for testing a tested object by an IC tester. The system has an operation rate means for calculating an operation rate in a prescribed period based on an operation data of the IC tester, and a charge calculating means for calculating a rental fee in the prescribed period, a desired period by a desired period, based on the operation rate from the operation rate means.
Inventors:
KATSUBE YASUHIRO
FUJII TAKASHI
FUJII TAKASHI
Application Number:
JP2002210689A
Publication Date:
February 19, 2004
Filing Date:
July 19, 2002
Export Citation:
Assignee:
YOKOGAWA ELECTRIC CORP
International Classes:
G01R31/28; G01R31/317; (IPC1-7): G01R31/317; G01R31/28
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