To provide a testing device in which an MCM (multi-chipt module) characteristic is effectively used, a memory is freely selected and the memory is tested with high precision in a short time.
A CPU control part 54A operates CPU 10A for testing with a bus B1 at the time of testing CPU 10A. A selector 58C selectively connects one of an MEMC (memory controller) core 40 or the CPU control part 54A to the bus B1. A bus releasing signal generating part 53A makes CPU 10A inactive at the time of testing the memory 20. A memory data comparing part 52A operates the memory 20 for testing with the bus B2 at the time of testing the memory 20 so that it is judged whether the memory is normal or not and judgement result is outputted through a test terminal E. The selectors 58m1-58m3 selectively connects one of the MEMC core 40 or the memory data comparing part 52 to the bus B2. A test control part 51A makes the memory and CPU execute a test operation based on a signal inputted from SCK.
NISHIKAWA YUKINOBU
WATABE TAKAHIRO
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