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Title:
TESTING METHOD FOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JPS57162189
Kind Code:
A
Abstract:

PURPOSE: To shorten the test time of a memory device by storing information indicating the position on an array in each ROM element and reading the information by specific addresses to test whether each ROM element is arranged in a correct array or not.

CONSTITUTION: In the testing method of a memory device 10 having an array 1 composing of plural ROM elements 100W114, 200W214 and 300W314 each of which has plural storing positions, a pair of addresses selected so that all the ROM elements can be selected at least once are set up and the information of a position to be occupied in the array 1 by the element included in a storing position to be selected by the pair of addresses is stored in the storing position. A testing device 11 reads out the information stored in the pair of addresses from the memory device 10 and compares the information with proposed positional information to test the position of the ROM elements on the array, shortening the test time of the memory device.


Inventors:
TOKUTAKE YOSHIO
Application Number:
JP4515781A
Publication Date:
October 05, 1982
Filing Date:
March 27, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F11/22; G11C29/00; G11C29/08; G11C29/56; (IPC1-7): G06F9/06; G06F11/00; G11C29/00
Domestic Patent References:
JPS5552599A1980-04-17



 
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