PURPOSE: To enable execution of a test also for an IC package wherein a chip for which a logic circuit model for simulation can not be prepared is mounted.

CONSTITUTION: A pattern generating means 102 which generates an input pattern and a simulation means 104 which prepares a simulation model wherein a logic circuit model of a chip of the own company mounted in an IC package and a chip on the market are made to exist mixedly, executes simulation for the simulation model by using the input pattern and determines an output value at an output terminal and a state value at an input/output pin of each chip, are provided. Moreover, a pin information extracting means 103 which extracts input/output pin information of each chip from the simulation model and a test pattern editing means 105 which outputs an output a test pattern showing an output value of the IC package for the input pattern and the state value at the input/output pin of each chip, on the basis of the result of the simulation by the simulation means 104, are provided.