Title:
薄膜トランジスタ表示板及びその製造方法
Document Type and Number:
Japanese Patent JP5324111
Kind Code:
B2
Abstract:
The disclosed thin film transistor array panel includes an insulating substrate, a channel layer including an oxide formed on the insulating substrate. A gate insulating is layer formed on the channel layer and a gate electrode is formed on the gate insulating layer. An interlayer insulating layer is formed on the gate electrode and a data line formed on the interlayer insulating layer and includes a source electrode, wherein the data line is made of a first conductive layer and a second conductive layer. A drain electrode formed on the interlayer insulating layer, and includes the first conductive layer and the second conductive layer. A pixel electrode extends from the first conductive layer of the drain electrode and a passivation layer formed on the data line and the drain electrode. A spacer formed on the passivation layer.
Inventors:
Lee system
Wiseness
Zheng Huan
Wiseness
Zheng Huan
Application Number:
JP2008058887A
Publication Date:
October 23, 2013
Filing Date:
March 10, 2008
Export Citation:
Assignee:
Samsung Display Co.,Ltd.
International Classes:
H01L29/786; G02F1/1362; H01L21/336; H01L29/417
Domestic Patent References:
| JP2007133371A | ||||
| JP2007081362A | ||||
| JP2005338796A | ||||
| JP6045604A | ||||
| JP2006216941A | ||||
| JP9311348A | ||||
| JP7159772A | ||||
| JP2004200638A |
Attorney, Agent or Firm:
Yamashita
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