Title:
薄膜トランジスタおよびその形成方法
Document Type and Number:
Japanese Patent JP2008522440
Kind Code:
A
Abstract:
A TFT includes a substrate and a first semiconductor layer overlying the substrate. A portion of the first semiconductor layer is a channel region of the TFT. The TFT also includes spaced-apart first and second source/drain structures overlying the first semiconductor layer. From a plan view of the TFT, the channel region lies between the first source/drain structure and the second source/drain structure. The TFT further includes a gate dielectric layer overlying the channel region and the first and second source/drain structures, and a gate electrode overlying the first gate dielectric layer. A process for forming the TFT includes forming first and second metal-containing structures over first and second semiconductor layers. The process also includes removing the portion of the second semiconductor layer lying between the first and second source/drain structures. A gate dielectric layer and a gate electrode are formed within the spaced-apart first and second source/drain structures.
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Inventors:
Jae Siun Run
Cancer you
Cancer you
Application Number:
JP2007544485A
Publication Date:
June 26, 2008
Filing Date:
November 30, 2005
Export Citation:
Assignee:
E.I.DU PONT DE NEMOURS AND COMPANY
International Classes:
H01L29/786; H01L51/50
Domestic Patent References:
| JPH0653506A | 1994-02-25 | |||
| JPH0682830A | 1994-03-25 |
Attorney, Agent or Firm:
Yoshikazu Tani
Kazuo Abe
Kazuo Abe