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Title:
THIN FILM TRANSISTOR MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2012119691
Kind Code:
A
Abstract:

To provide a thin film transistor which ensures excellent productivity as well as having excellent properties and a highly reliable gate insulation layer, and to provide a manufacturing method of the same.

A thin film transistor including, on a substrate 9, an active layer 11 having a source region 17, a channel region 18 and a drain region 19, a gate electrode layer 16, and a gate insulation layer 15 formed between the active layer 11 and the gate electrode layer 16. The gate insulation layer 15 is formed of a first silicon oxide film 12 formed on the side of the active layer 11, a second silicon oxide film 14 formed on the side of the gate electrode layer 16, and a silicon nitride film 13 formed between the first silicon oxide film 12 and the second silicon oxide film 14.


Inventors:
WAKAMATSU TEIJI
KIKUCHI TORU
HASHIMOTO YUKINORI
KURATA TAKAOMI
ASARI SHIN
SAITO KAZUYA
Application Number:
JP2011278653A
Publication Date:
June 21, 2012
Filing Date:
December 20, 2011
Export Citation:
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Assignee:
ULVAC CORP
International Classes:
H01L29/786; G02F1/1368; H01L21/316; H01L21/318; H01L21/336; H01L29/49
Domestic Patent References:
JPH07235530A1995-09-05
JP2003142496A2003-05-16
JP2000150389A2000-05-30
JP2001102322A2001-04-13
JP2000243802A2000-09-08
JP2001237237A2001-08-31
JP2001135824A2001-05-18
Attorney, Agent or Firm:
Yoshihiro Shimizu
Shinichi Abe
Yuji Tsujida



 
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