Title:
TIME AXIS CORRECTING DEVICE
Document Type and Number:
Japanese Patent JP2728586
Kind Code:
B2
Abstract:
PURPOSE: To eliminate jitters including the velocity error of an input signal over the whole of 1H by following the velocity error of the input signal while changing the frequency and accurately synchronizing with the phase of the input signal over the whole of 1H of the input signal.
CONSTITUTION: Input signal data (e) digitalized by a write clock signal WCK in an A/D converter 8 is written in a memory 10 according to the address specified by a write address counter 9. Then the input signal data (e) of the memory 10 is read out from the memory 10 according to the address specified by a read address counter 11 based on the stable reference clock signal for reading, further made into an analog signal by a D/A converter 12. With respect to the analog output signal jitters including the velocity error is accurately corrected and removed by a write clock signal WCK over 1H and the signal becomes highly stable in terms of time.
Inventors:
SUZUKI TAKEO
HASHIMOTO MAKOTO
KOIDE TAKESHI
HASHIMOTO MAKOTO
KOIDE TAKESHI
Application Number:
JP32192091A
Publication Date:
March 18, 1998
Filing Date:
December 05, 1991
Export Citation:
Assignee:
SHAAPU KK
International Classes:
H04N5/956; H04N5/95; H04N9/89; H04N9/896; (IPC1-7): H04N9/896; H04N5/956
Domestic Patent References:
| JP2162983A |
Attorney, Agent or Firm:
Kenzo Hara