To replace a time slot of a multiplexed signal without limiting a speed of a clock signal of an input multiplex signal and that of an output multiplex signal to be a same speed.

Each bit string of an input multiplex signal 200 is stored in a speech memory section 12 according to a write address signal 100 fed from a control memory 14, the bit string is read according to a read address signal 102 and an output multiplex signal 206 is outputted. The write address signal 100 is address information to attain random write or sequential write to the speech memory section 12 and the read address signal 102 is address information making random read or sequential read to the speech memory section 12 and the signal 100 is generated by a 1st control memory section 18 corresponding to the clock speed of the input multiplex signal depending on a mode signal 210 and the signal 102 is generated by a 2nd control memory section 20 corresponding to the clock speed of an output multiplex signal 206.