Title:
バイアス電流補償回路を有するタイミング発生器及び方法
Document Type and Number:
Japanese Patent JP4842131
Kind Code:
B2
Abstract:
A current compensation circuit for use with a current mirror is disclosed. The current mirror circuit has a current path defined by a first current mirror stage driving a second current mirror stage, the second current mirror stage is coupled to a supply voltage source. The current compensation circuit comprises an impedance divider coupled to the supply voltage and an output node. The impedance divider operates to generate a compensation signal at the node representative of voltage changes in the supply voltage source. The compensation circuit further includes a gain stage having an input coupled to the output node and a current output connected to the current path. The gain stage operates to generate a compensation current for application to the current path in response to the compensation signal.
Inventors:
Iloga, Echele
Application Number:
JP2006528209A
Publication Date:
December 21, 2011
Filing Date:
September 25, 2004
Export Citation:
Assignee:
TERADYNE INCORPORATED
International Classes:
H03L7/093; G01R31/3183; G05F3/26; H03K5/13; H03K5/135; H03L7/081; H03L7/089; H03K5/00
Domestic Patent References:
| JPH09326689A | 1997-12-16 | |||
| JP2003023354A | 2003-01-24 | |||
| JP2003264452A | 2003-09-19 | |||
| JPH08130449A | 1996-05-21 | |||
| JP2002171165A | 2002-06-14 | |||
| JPH1197949A | 1999-04-09 | |||
| JPH0926465A | 1997-01-28 | |||
| JPH1093406A | 1998-04-10 | |||
| JPH11251844A | 1999-09-17 | |||
| JPH01226015A | 1989-09-08 | |||
| JPH11340760A | 1999-12-10 | |||
| JPH07141865A | 1995-06-02 |
Attorney, Agent or Firm:
Shinjiro Ono
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Otsuka Naruhiko
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Otsuka Naruhiko