PURPOSE: To simplify greatly the constitution of a timing pulse generating circuit by using a serial-in/parallel-out shift register circuit and a JK flip-flop circuit and eliminating the need for a click signals of two phases.

CONSTITUTION: The head output 01 of a parallel output pulse is produced from an asynchronous start signal 112 which is supplied to a serial-in/parallel-out shift register circuit 5. This head output is supplied to a JK flip-flop circuit 4. The output 402 given from a Q output terminal and the signal 112 are defined as two inputs IN1 and IN2 of the circuit 5 respectively, and an AND of these inputs is shifted by a clock signal 111. A cycle of the clock signal is defined as the pulse width, and a timing pulse 203 is obtained as a parallel output pulse that is obtained synchronously with the clock pulse.