Title:
ONE-BIT MICROPROCESSOR
Document Type and Number:
Japanese Patent JPS6014368
Kind Code:
A
Abstract:
PURPOSE:To actuate a multi-stage counter with a small number of memories by providing a data bus different from a normal data bus for exchange of data between a presettable internal counter and a data momory. CONSTITUTION:A data memory 15 is connected to an internal counter 16 with a data bus 19 different from a normal data bus. In a counting mode a counter loading instruction is executed to load data to a counter 16. The counter 16 has a counting action in accordance with the loaded data and stores the count result to both the memory 15 and a result register 17. Thus the addresses are updated for each instruction in a program memory 13. In such a way, a multi-stage counter can be actuated witha small number of memories by using the bus 19 for connection between the counter 16 and the memory 15.
Inventors:
YASUI TOSHIO
Application Number:
JP12126683A
Publication Date:
January 24, 1985
Filing Date:
July 04, 1983
Export Citation:
Assignee:
NIPPON DENSO CO
International Classes:
G06F7/00; G06F9/305; G06F9/38; G06F15/78; H03K21/00; (IPC1-7): G06F15/06; G06F7/00; H03K21/00
Attorney, Agent or Firm:
Takehiko Suzue