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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH07106514
Kind Code:
A
Abstract:

PURPOSE: To reduce loss due to electrostatic capacity and suppress the drop in Q factor due to electrical resistance by providing inductance from a plurality of laminated spiral metallic wiring layers through insulation films on a semiconductor substrate.

CONSTITUTION: An inductance 10 is produced with a plurality of layers including a first spiral metallic wiring layer 16 and a second spiral metallic wiring layer 20 within the same forming process for transistor and other circuit element to be formed on a semiconductor substrate 11. And the inductance 10 comprises both the spiral metallic wiring layers 16 and 20 and a metal embedded layer 19 for connecting these, and the facing surface to the semiconductor substrate 11 through a first interlayer insulation film 14 is only the bottom surface of the first spiral metallic wiring layer 16. Therefore, even though the pattern of the first spiral metallic wiring layer 16 is made finer and the electrostatic capacity is reduced, its electric resistance does not increase.


Inventors:
HIRAKAWA KENJI
Application Number:
JP25088593A
Publication Date:
April 21, 1995
Filing Date:
October 07, 1993
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L21/822; H01L23/64; H01L27/04; (IPC1-7): H01L27/04; H01L21/822
Attorney, Agent or Firm:
Norio Ogo