【発明の名称】原子アクセス制御レジスタ装置

Title:

【発明の名称】原子アクセス制御レジスタ装置

Document Type and Number:

Japanese Patent JP3381733

Kind Code:

B2

Abstract:

A computer storage register architecture permitting secure atomic access to set or dear one or more particular bits wherein a multiple bit register is diclosed. In the preferred embodiment, a multiplicity of unique addresses is assigned to a multiple bit register. One address constitutes a read address, one address constitutes a clear address, and a third address constitutes a set address. An address decoder decodes the addresses assigned to the register so that only that register is accessed for the associated read, clear, and set operations, respectively. Data having a register position equivalent binary pattern of logical zeros and ones corresponding to particular bit locations of the register to be set or cleared are associated with the set and clear addresses. If the position equivalent binary value of the data associated with the address decoded is a logical one, then the corresponding bit in the register will be set or cleared. Otherwise, the bit remains unchanged.

Inventors:

Charles E Narad

Application Number:

JP28234292A

Publication Date:

March 04, 2003

Filing Date:

September 28, 1992

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