Title:
【発明の名称】CMOSマルチプライヤ
Document Type and Number:
Japanese Patent JP3127846
Kind Code:
B2
Abstract:
An analog multiplier that decreases the circuit current consumption is provided. This multiplier includes a first triple-tail cell of first, second, and third transistors driven by a first tail current, and a second triple-tail cell of fourth, fifth, and sixth transistors driven by a second tail current. First and second constant current sources supplies first and second constant currents to the third and sixth transistors, respectively. The first and second tail currents are controlled by first and second tail current controllers, respectively The first and second tail current controllers controls the first and second tail currents so that the current changes of the third and sixth transistors are canceled, respectively, where the current changes are caused by the second input voltage applied across the input terminals of the third and sixth transistors.
Inventors:
Katsuji Kimura
Application Number:
JP32785896A
Publication Date:
January 29, 2001
Filing Date:
November 22, 1996
Export Citation:
Assignee:
NEC
International Classes:
G06G7/163; G06G7/164; (IPC1-7): G06G7/163
Domestic Patent References:
| JP8315056A | ||||
| JP883314A | ||||
| JP757026A | ||||
| JP2502409A |
Attorney, Agent or Firm:
Asamichi Kato