Title:
【発明の名称】キャッシュメモリシステムおよびキャッシュメモリコントローラ
Document Type and Number:
Japanese Patent JP3192664
Kind Code:
B2
Abstract:
A cache memory system for controlling a cache memory. The cache memory system is connected to a central processing unit and a main memory and the cache memory system is controlled to operate in a copyback operation mode. The cache memory system includes the cache memory which operates as cache memory to the central processing unit and a control circuit, responsive to detection of an error in the cache memory, for suspending an updating operation of an entry in the cache memory in which the error was detected, controlling access to valid entries in the cache memory, and causing the cache memory to operate as cache memory only when access from the central processing unit hits the valid entries of the cache memory.
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Inventors:
Koichi Okazawa
Kazushi Kobayashi
Kazuharu Yuno
Kazushi Kobayashi
Kazuharu Yuno
Application Number:
JP595891A
Publication Date:
July 30, 2001
Filing Date:
January 22, 1991
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
G06F12/08; G06F12/12; G06F12/16; G11C29/00; (IPC1-7): G06F12/08; G06F12/12; G06F12/16
Domestic Patent References:
| JP55122287A | ||||
| JP289145A | ||||
| JP5644181A | ||||
| JP1318129A | ||||
| JP51113427A | ||||
| JP54150042A | ||||
| JP55157180A | ||||
| JP57179999A | ||||
| JP63129440A | ||||
| JP227440A | ||||
| JP312753A |
Attorney, Agent or Firm:
Kazuko Tomita