Title:
【発明の名称】回路シミュレーション装置及び記録媒体
Document Type and Number:
Japanese Patent JP3336996
Kind Code:
B2
Abstract:
A device for simulating circuits is provided with an identifying system and a verifying system. The identifying system identifies a pair of wires in which two signals operate simultaneously within an appointed period and a pair of wires in which two signals do not operate almost simultaneously within the appointed period. The verifying system verifies actions of a circuit to be analyzed, under an assumption that the coupling capacitor between the pair of wires in which it is judged by the identifying system that two signals do not simultaneously operate within the appointed period is a ground capacitor.
Inventors:
Mitsuru Sato
Application Number:
JP13634499A
Publication Date:
October 21, 2002
Filing Date:
May 17, 1999
Export Citation:
Assignee:
NEC
International Classes:
G06F9/45; G06F17/50; G01R31/28; G06G7/62; H01L21/82; (IPC1-7): G06F17/50
Domestic Patent References:
| JP11154709A | ||||
| JP11275176A | ||||
| JP10207937A | ||||
| JP8221460A | ||||
| JP7182405A | ||||
| JP798727A | ||||
| JP6120343A | ||||
| JP4241068A |
Attorney, Agent or Firm:
Masanori Fujimaki