Title:
【発明の名称】電流乗算・割算回路
Document Type and Number:
Japanese Patent JP2956610
Kind Code:
B2
Abstract:
A current multiplier/divider circuit is provided, which is capable of any one of multiplication and division operations in a current mode without changing its configuration. This circuit includes a first set of m bipolar transistors and a second set of n bipolar transistors, where m>/=2) and n>/=2. A base of a (j-1)-th one of the transistors of the first set is connected to an emitter of the j-th transistor of the first set, where 2=j=m. A base of a (k-1)-th one of the transistors of the second set is connected to an emitter of the k-th transistor of the second set, where 2=k=n. A sum of VBE of the m transistors with respect to a specific electric potential, which is generated at a base of the m-th transistor in the first set, is equal to a sum of VBE of the n transistors, which is generated at a base of the n-th transistor in the second set. At least one of collector currents of the (m+n) transistors in the first and second sets is used as an input current, at least one of these collector currents are used as an output current, and he remaining collector currents are set as constant currents, respectively. The at least one output current includes the multiplication or division result of the at least one input.
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Inventors:
KIMURA KATSUHARU
Application Number:
JP24891996A
Publication Date:
October 04, 1999
Filing Date:
August 30, 1996
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G06G7/16; G06G7/163; (IPC1-7): G06G7/16
Domestic Patent References:
JP375977A | ||||
JP551458A | ||||
JP6120810A | ||||
JP6188322U |
Attorney, Agent or Firm:
Asato Kato