Title:
【発明の名称】高速データスイッチ用データパケット再順番付け装置
Document Type and Number:
Japanese Patent JP2769746
Kind Code:
B2
Abstract:
A resequencing buffer and buffer control circuit is disclosed for resequencing data packets into their timed sequence after traversing a switch fabric which can introduce a misordering of data packets because of the varying time intervals required for data packets to traverse the switch fabric in a non-blocking manner. The resequencing buffer controller includes a plurality of hi-directional shift registers for storing each data packet's age and slot number, each bi-directional shift register having an associated slot control circuit for feeding the age and slot number one bit at a time onto a contention bus to thereby determine the oldest data packet eligible for transmission. The contention bus is an exclusive OR wire bus which interconnects the slot control circuits and an output circuit which controls the buffer to output the slot number containing the data packet of oldest age. In the event of ties between data packets having the same age, the slot numbers of the buffer are used to select a data packet for transmission.
Inventors:
Turner Jonathan S
Application Number:
JP50816892A
Publication Date:
June 25, 1998
Filing Date:
February 13, 1992
Export Citation:
Assignee:
Washington University
International Classes:
H04Q3/00; H04L12/56; H04Q3/52; H04Q11/04; (IPC1-7): H04L12/56; H04Q3/52
Domestic Patent References:
| JPH02195758A | 1990-08-02 | |||
| JPH02206258A | 1990-08-16 | |||
| JPH01170144A | 1989-07-05 | |||
| JPH03255748A | 1991-11-14 |
Attorney, Agent or Firm:
Hiroo Suzuki