Title:
【発明の名称】電気発破用遅延回路
Document Type and Number:
Japanese Patent JP2572797
Kind Code:
B2
Abstract:
A delay circuit for use in an electric blasting system including a capacitor for storing electric energy supplied from an electric blaster, an actuation circuit for detecting the stop of voltage supply from the blaster to generate an actuation signal, a circuit for generating clock pulses, a circuit for counting a predetermined number of clock pulses in response to the actuation signal to generate an igniting signal, and a switching circuit for responding to the igniting signal to discharge the electric energy stored in the capacitor through an igniting resistor, the actuation circuit having a zener diode with a threshold voltage. When the voltage supply from the blaster is stopped and the voltage across the zener diode becomes lower than the threshold voltage, the zener diode is cut-off to generate the actuation signal.
Inventors:
OCHI KOJI
HARADA TSUKUHIDE
KOBAYASHI KUNIO
HARADA TSUKUHIDE
KOBAYASHI KUNIO
Application Number:
JP3186988A
Publication Date:
January 16, 1997
Filing Date:
February 16, 1988
Export Citation:
Assignee:
NIPPON YUSHI KK
HARADA DENSHI KOGYO KK
HITACHI SEISAKUSHO KK
HARADA DENSHI KOGYO KK
HITACHI SEISAKUSHO KK
International Classes:
F42B3/16; F42B3/18; F42C11/06; F42D1/055; F42D1/06; H03K5/135; (IPC1-7): F42B3/16; F42C11/06; F42D1/06
Domestic Patent References:
| JP6383599A |
Attorney, Agent or Firm:
Akihide Sugimura (1 outside)