Title:
【発明の名称】ヒューリスティックプロセッサ
Document Type and Number:
Japanese Patent JP2862671
Kind Code:
B2
Abstract:
A heuristic processor incorporates a digital arithmetic unit arranged to compute the squared norm of each member of a training data set with respect to each member of a set of centers, and to transform the squared norms in accordance with a nonlinear function to produce training phi vectors. A systolic array arranged for QR decomposition and least mean squares processing forms combinations of the elements of each phi vector to provide a fit to corresponding training answers. The form of combination is then employed with like-transformed to provide estimates of unknown result. The processor is applicable to provide estimated results for problems which are nonlinear and for which explicit mathematical formalisms are unknown.
Inventors:
BURUUMETSUDO DEIBITSUDO SHIDONII
JOONZU ROBIN
SHEPAADO TERENSU JON
MATSUKUAATAA JON GUREIAMU
JOONZU ROBIN
SHEPAADO TERENSU JON
MATSUKUAATAA JON GUREIAMU
Application Number:
JP50268590A
Publication Date:
March 03, 1999
Filing Date:
January 31, 1990
Export Citation:
Assignee:
IGIRISU
International Classes:
G06G7/60; G06F15/18; G06N3/02; G06N3/10; G06N99/00; (IPC1-7): G06F15/18
Other References:
Ｃｏｍｐｕｔｅｒ Ｖｏｌ．２０，ｎｏ．７ Ｊｕｌｙ １９８７ ｐ５１−６３
Ｃｏｎｆｅｒｅｎｃｅ Ｐｒｏｃｅｅｄｉｎｇｓ，Ｍｉｌｉｔａｒｙ Ｍｉｃｒｏｗａｖｅｓ’８８ ｐ５２１−５２６
Ｐｒｏｃｅｅｄｉｎｇｓ ＩＥＥＥ Ｉｎｔｅｒｎａｔｉｏｎａｌ Ｃｏｎｆｅｒｅｎｃｅ ｏｎ Ｎｅｕｒａｌ Ｎｅｔｗｏｒｋｓ ２４−２７ Ｊｕｌｙ １９８８ ｐ３４９−３５６
Ｐｒｏｃｅｅｄｉｎｇｓ Ｉｎｔｅｒｎａｔｉｏｎａｌ Ｃｏｎｆｅｒｅｎｃｅ ｏｎ Ｓｙｓｔｏｌｉｃ Ａｒｒａｙｓ ２５−２７ Ｍａｙ １９８８ ｐ１６３−１７４
Ｃｏｎｆｅｒｅｎｃｅ Ｐｒｏｃｅｅｄｉｎｇｓ，Ｍｉｌｉｔａｒｙ Ｍｉｃｒｏｗａｖｅｓ’８８ ｐ５２１−５２６
Ｐｒｏｃｅｅｄｉｎｇｓ ＩＥＥＥ Ｉｎｔｅｒｎａｔｉｏｎａｌ Ｃｏｎｆｅｒｅｎｃｅ ｏｎ Ｎｅｕｒａｌ Ｎｅｔｗｏｒｋｓ ２４−２７ Ｊｕｌｙ １９８８ ｐ３４９−３５６
Ｐｒｏｃｅｅｄｉｎｇｓ Ｉｎｔｅｒｎａｔｉｏｎａｌ Ｃｏｎｆｅｒｅｎｃｅ ｏｎ Ｓｙｓｔｏｌｉｃ Ａｒｒａｙｓ ２５−２７ Ｍａｙ １９８８ ｐ１６３−１７４
Attorney, Agent or Firm:
Yoshio Kawaguchi (4 outside)