Title:
【発明の名称】積分回路
Document Type and Number:
Japanese Patent JP3167130
Kind Code:
B2
Abstract:
An integrator circuit for input signals in the form of sampled analogue currents has an input connected to a node (2). Also connected to the node (2) are a first current memory cell (C1, T1, S2) and a second current memory cell (C2, T2, T3, S3). The switches (S1, S3) are operated on opposite phases of a clock signal synchronised with the sampling period. The first current memory cell produces an output current when switch (S2) is open while the second current memory cell produces a first output when switch (S3) is open and a second output (T3) which is connected to the output (6) of the integrator and which is continuously available. Forward or Backward Euler mapping is produced by closing switch (S1) on appropriate phases of the clock. A Bilinear mapping can be produced by connecting an inverted version of the input signal to a second input (8) and appropriately clocking the switches (S1, S4). A feedforward function can be added by use of a further input (9) directly connected to the node (2). Various higher performance current memory cells are also disclosed together with fully differential versions of the integrator.
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Inventors:
John Barry Hughes
Application Number:
JP20692290A
Publication Date:
May 21, 2001
Filing Date:
August 06, 1990
Export Citation:
Assignee:
Konin Krekka Philips Electronics NV
International Classes:
G06G7/18; G06G7/184; G11C27/02; H03M1/08; H03M1/74; (IPC1-7): G06G7/18; H03M1/08
Domestic Patent References:
| JP33515A |
Attorney, Agent or Firm:
Susumu Tsugaru (6 people outside)