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Patent Searching and Data


Title:
MEMORY CONTROLLER OF ELECTRONIC COMPUTER
Document Type and Number:
Japanese Patent JPS5922154
Kind Code:
A
Abstract:

PURPOSE: To eliminate an error of a program and to operate an electronic computer efficiently by performing exclusive control automatically when plural programs access a common global area.

CONSTITUTION: A locking circuit 2 is connected to respective arithmetic controllers. When data in the global area 6 is made access, the address in an instruction is led out of an address extracting circuit 10 and inputted to a lock checking circuit 11. The circuit 11 inhibits a gate circuit 14 from being open until access to an address is completed when the address to be made access is in the global area 6 and by another controller 1. Further, when access to the global area 6 is possible and the address to be made access is not in the global area 6, a gate-on signal is outputted to the circuit 14. Therefore, only one arithmetic device 1 is permitted to be in access to the global area.


Inventors:
ASANUMA AKIO
OOHASHI TADAHIRO
Application Number:
JP13240382A
Publication Date:
February 04, 1984
Filing Date:
July 29, 1982
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G06F12/00; G06F9/46; G06F9/52; (IPC1-7): G06F9/34; G06F13/00
Attorney, Agent or Firm:
Kiyoshi Inomata