Title:
【発明の名称】LSIテスト方法
Document Type and Number:
Japanese Patent JP3119474
Kind Code:
B2
Abstract:
PURPOSE:To enhance the detection ratio of unrecoverable trouble by setting an LSI to be tested to a test mode statistically and suppressing an IC other than the LSI to be tested to the min. in an acceleration tester to activate the greater part of the gates of the LSI to be tested. CONSTITUTION:A test board 103 wherein an LSI 201 to be tested and a clock signal generator 104 are mounted and wiring is applied is introduced into an acceleration tester 101 to set acceleration test environment by a control part 102. Whereupon, the LSI 201 becomes a test mode because a mode terminal is active at the time of power-on-reset and performs internal operation without accessing to the test board 103. By this method, a part other than the clock signal generator 104 is unnecessary on the test board. Further, the greater part of the gates in the LSI 201 are activated and an acceleration test can be performed.
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Inventors:
Hisao Hariya
Application Number:
JP24603088A
Publication Date:
December 18, 2000
Filing Date:
September 29, 1988
Export Citation:
Assignee:
NEC
International Classes:
G01R31/30; G01R31/3183; H01L21/66; G01R31/28; (IPC1-7): G01R31/28; G01R31/30; G01R31/3183; H01L21/66
Domestic Patent References:
| JP6378077A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)