Title:
【発明の名称】対数増幅回路
Document Type and Number:
Japanese Patent JP2995886
Kind Code:
B2
Abstract:
A logarithmic amplification circuit is provided which comprises a differential amplifier (A1...An), a full-wave rectifier (B0...Bn) including two half-wave rectifiers connected so as to have their input signals reverse in phase to each other and respectively receiving an input signal and output signal of said differential amplifier, and an adder (ADD) for adding the output signals of said full-wave rectifier. It is preferable that each of the half-wave rectifiers forming said full-wave rectifier (B0...Bn) includes a differential transistor pair only one transistor of which has an emitter resistor. In this case, two sets of differential transistor pairs of said two half-wave rectifiers are arranged so that the transistors each having an emitter resistor have their collectors connected with each other, the transistors not having an emitter resistor have their collectors connected with each other, one of an output signal and input signal of said differential amplifier is applied to the base of one of the transistors each having an emitter resistor and one of the transistors each not having an emitter resistor, the other of an output signal and input signal of said differential amplifier is applied to the base of the other of the transistors each having an emitter resistor and the other of the transistors each not having an emitter resistor, and the transistors of each pair are connected respectively to constant current sources. In the preferred embodiments of this invention, said differential amplifier (A1...An) is provided plurally in a series connection and the input signals or output signals of these plural differential amplifiers are inputted to a plurality of rectifiers (B0...Bn) in a respective manner.
Inventors:
Kimura
Application Number:
JP5791891A
Publication Date:
December 27, 1999
Filing Date:
February 28, 1991
Export Citation:
Assignee:
NEC
International Classes:
H03G7/00; G06G7/24; H03G7/06; H03G11/08; (IPC1-7): H03G11/08
Domestic Patent References:
| JP2265310A | ||||
| JP1261008A | ||||
| JP62293807A |
Attorney, Agent or Firm:
Naoki Kyomoto