Title:
【発明の名称】中央演算処理装置の調停回路
Document Type and Number:
Japanese Patent JP2870837
Kind Code:
B2
Abstract:
PURPOSE:To continue the processing operation of an external device connected to a central processing unit (CPU) and to prevent the generation of malfunction by generating a response signal corresponding to a holding circuit even when the CPU is abnormally stopped. CONSTITUTION:When the CPU 8 is normally operated, the level of a reset signal is OFF. Thereby the gate of an AND circuit 23 is closed. If abnormality occurs in the CPU 8 and the CPU 8 is reset by a watch-dog timer circuit 11, the gate of the circuit 23 is opened because the level of the reset signal is held at ON. When a HOLD signal is generated by a directly connected I/O bus interface 6, the ON HOLD signal is successively transferred in the order of the circuit 23 OR circuit 22 HLDA terminal of interface 6. Thereby, the interface 6 can write/read out information signals in/from a static RAM 10. Since the CPU 8 is in the reset state, interference is not generated in the bus 7.
Inventors:
YATSUDA YUTAKA
Application Number:
JP21752389A
Publication Date:
March 17, 1999
Filing Date:
August 25, 1989
Export Citation:
Assignee:
FUJI DENKI KK
International Classes:
G06F13/42; G06F11/00; G06F13/00; G06F13/28; (IPC1-7): G06F13/28
Domestic Patent References:
| JP62150454A | ||||
| JP61213960A | ||||
| JP62281044A | ||||
| JP4975238A |
Attorney, Agent or Firm:
Yoshikazu Tani