Title:
【発明の名称】メモリアクセス制御装置
Document Type and Number:
Japanese Patent JP2594567
Kind Code:
B2
Abstract:
PURPOSE:To speed up abnormality processing by deciding whether an address in a data buffer (MAB) for storing read data coincides with a MAB for storing write data or not when a write request is abnormally ended by some reason before generating a read request, and when both the addresses coincide with each other, information abnormal end without waiting the read request. CONSTITUTION:When a port receives a request, the port status goes to a priority order waiting state. A port controller (PC) selects a port with the highest priority out of the priority waiting ports and outputs a request to a memory control unit (MCU). Data returned to the MCU by accessing a main memory (MSU) from the MCU are returned to the port controller (PC). The port controller (PC) decides whether the executed processing is normal or abnormal independently of the coincidence/discrepancy of the MAB address. At the time of abnormal end, the port status is abnormally ended and an abnormal end code is sent by another request.
Inventors:
Hiroyuki Egawa
Kimura Makoto
Kimura Makoto
Application Number:
JP19997587A
Publication Date:
March 26, 1997
Filing Date:
August 12, 1987
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F12/08; G06F12/00; G06F12/06; G06F12/16; (IPC1-7): G06F12/16; G06F12/06
Domestic Patent References:
| JP5169615A |
Attorney, Agent or Firm:
Aoki Akira (3 outside)