Title:
SIGNAL PROCESSOR FOR CORRECTING DISTORTION OF DISPLAY IMAGE
Document Type and Number:
Japanese Patent JPH066758
Kind Code:
A
Abstract:
PURPOSE: To obtain a signal processing device for the line synchronizing pulse of a line synchronizing signal for limiting an analog video signal line period. CONSTITUTION: This signal processing device has a phase-locked loop 40 for generating a clock signal having a frequency being the multiple of line synchronizing signal frequency. The phaselocked loop 40 has a counter 100 for dividing the clock signal into the multiple. The signal processing device further has logic circuits 110 and 50 for resetting the counter 100 after detecting a spurious pulse for leading a time interval into a line synchronizing signal having a shorter line period than that of a video signal. The signal processing device is especially useful for a picture processing system for digitalizing an analog video signal reproduced by a conventional video tape player, and even if the video signal includes a spurious line synchronizing pulse generated by the skip of a reproducing head, the image is not distorted.
Inventors:
TOOMASU UIRIAMU RIKAADO
PIITAA MAATEIN SUMISU
DEBITSUDO CHIYAARUZU KONUEIIJI
DEBITSUDO JIYON BURAUN
PIITAA MAATEIN SUMISU
DEBITSUDO CHIYAARUZU KONUEIIJI
DEBITSUDO JIYON BURAUN
Application Number:
JP33416792A
Publication Date:
January 14, 1994
Filing Date:
December 15, 1992
Export Citation:
Assignee:
IBM
International Classes:
G11B20/02; G11B20/22; H03L7/199; H04N5/93; H04N5/932; (IPC1-7): H04N5/93; G11B20/02; G11B20/22
Domestic Patent References:
| JPS56136091A | 1981-10-23 | |||
| JPS61274479A | 1986-12-04 |
Attorney, Agent or Firm:
Koichi Tonmiya (4 outside)
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