Title:
【発明の名称】ニューラルネットワークの構築方法
Document Type and Number:
Japanese Patent JP2862337
Kind Code:
B2
Abstract:
PURPOSE:To reduce the scale of a circuit by substituting multiplication in the neuron of a neural network for bit shift and the sum of bit-shifted data. CONSTITUTION:One line in inputted binary data is delayed in a line buffer LB, and another one line is delayed in a line buffer LB 2. Data which is not delayed, data delayed by one line and two lines are latched by latches LT3-5 and they are delayed by one picture element. The outputs are delayed by one picture element by latches LT 6-8 and they are turned into binary PT data. Binary PT data is inputted to an intermediate part. The intermediate part executes an operation by bit shift and addition and the output is inputted to multipliers. The weight coefficient Wkj of an output layer is multiplied and the outputs of respective multipliers are added in an adder.
Inventors:
MITA YOSHINOBU
Application Number:
JP16190490A
Publication Date:
March 03, 1999
Filing Date:
June 19, 1990
Export Citation:
Assignee:
KYANON KK
International Classes:
G06G7/60; G06F15/18; G06N3/04; G06N99/00; (IPC1-7): G06F15/18
Domestic Patent References:
| JP259854A |
Other References:
【文献】山田,柳生,益田,正木,平井,「大規模ニューラルネットワーク向けハードウェア方式」情報処理学会第38回(平成元年度前期)全国大会講演論文集(▲III▼)p.1526-p.1527(1989)
Attorney, Agent or Firm:
Giichi Marushima (1 person outside)