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Patent Searching and Data


Title:
LAYOUT PATTERN VERIFICATION DEVICE
Document Type and Number:
Japanese Patent JPH0634692
Kind Code:
A
Abstract:

PURPOSE: To highlight a part which is wired improperly by automatically retrieving the part which is wired improperly according to comparison results of connection information of a reference circuit and circuits to be compared.

CONSTITUTION: A means 9 for extracting connection information between pins retrieves all elements which are related to a signal corresponding to an mismatch signal S from connection information A1 and B1, connection information A4 and B4 between pins regarding the elements is created and output, and then it is given to a connection information comparison/verification means 10 between pins. The verification means 10 compares and verifies the connection information A4 and B4 between pins by referring to a correspondence table C2 of connection information, outputs an improperly wired part data D, and then gives it to a pin probing means 4. The pin probing means 4 outputs a data needed for highlighting the improper wiring to a display means based on the data D, the mismatch information specified by a signal element specification means, the connection information A1 and B1, and the correspondence table C2 and then highlights them.


Inventors:
ARITA SHINJI
Application Number:
JP19086992A
Publication Date:
February 10, 1994
Filing Date:
July 17, 1992
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G01R31/02; G06F17/30; G06F17/50; H01L21/66; (IPC1-7): G01R31/02; G06F15/40; H01L21/66
Attorney, Agent or Firm:
Takada Mamoru