Title:
【発明の名称】逓倍回路
Document Type and Number:
Japanese Patent JP2845178
Kind Code:
B2
Abstract:
A frequency multiplier circuit that needs no coupling capacitors and no input bias circuits for a next-stage circuit, which includes a phase-shifted signal generator, first and second differential amplifiers, and a multiplier. The phase-shifted signal generator receives an initial input signal and generates first and second output signals whose phases are shifted by 90 DEG with each other. The first differential amplifier amplifies the first output signal to output a first positive-phase output signal and a first negative-phase output signal. The second differential amplifier amplifies the second output signal to output a second positive-phase output signal and a second negative-phase output signal. The multiplier multiplies the first and second positive-phase output signals to output a third positive-phase output signal as a positive-phase output of the frequency multiplier circuit. At the same time, it multiplies the first and second negative-phase output signals to output a third negative-phase output signal as a negative-phase output of the frequency multiplier circuit. Each of the third positive- and negative-phase output signals has a doubled frequency of the initial input signal and substantially the same dc offset voltage.
Inventors:
HIRATA MASARU
Application Number:
JP22857195A
Publication Date:
January 13, 1999
Filing Date:
August 14, 1995
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G06G7/161; H03B19/00; H03B19/14; H03D7/12; H03D7/14; H03H7/18; (IPC1-7): H03B19/14; G06G7/161; H03D7/12; H03H7/18
Domestic Patent References:
| JP8116215A | ||||
| JP7135424A | ||||
| JP62264705A |
Other References:
ＬＥＥＥ Ｔｒａｎｓａｃｔｉｏｎ ｏｎ Ｍｉｃｒｏｗａｖｅ Ｔｈｅｏｒｙ ａｎｄ Ｔｅｃｈｎｉｑｕｅｓ，ｖｏｌ．３８，ｎｏ．９，Ｓｅｐ．１９９０，ｐａｇｅｓ １１９４−１１９５，”Ｍｕｌｔｉｆｕｎｃｔｉｏｎ Ｓｉｌｉｃｏｎ ＭＭＩＣ’ｓ ｆｏｒ Ｆｒｅｑｕｅｎｃｙ Ｃｏｎｖｅｒｓｉｏｎ Ａｐｐｌｉｃａｔｉｏｎｓ”，Ｋｅｖｉｎ Ｊ．Ｎｅｇｕｓ
Attorney, Agent or Firm:
Suzuki Akio