Title:
【発明の名称】神経回路
Document Type and Number:
Japanese Patent JP3100610
Kind Code:
B2
Abstract:
PURPOSE:To obtain a circuit to be easily formed as an LSI with small hardware size by providing the neural circuit with memories capable of respectively storing values corresponding to film potential, excitable input and an inhibiting input and modeling the neural circuit by a digital circuit. CONSTITUTION:The 1st memory 101 stores a value corresponding to film potential in each neural unit. A 2nd memory 103 stores a value for changing the value corresponding to the film potential in accordance with an excitable input and an inhibiting input. A time division control circuit 113 accesses a value of each remarked neural unit in the memories 101, 103. A film potential change corresponding to the excitable input and the inhibiting input is simulated by a part constituted of the memories 101, 103 and an adder part 107. A film potential change obtained when none of the excitable and inhibiting inputs exists is simulated by a part constituted of the adder part 107 and a bit shifting/ inverting circuit 111. An output pulse is simulated by a decision circuit part 109.
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Inventors:
Atsushi Shimbo
Hideki Kamoi
Hiroshi Imai
Hiromi Ando
Hideki Kamoi
Hiroshi Imai
Hiromi Ando
Application Number:
JP18444490A
Publication Date:
October 16, 2000
Filing Date:
July 12, 1990
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
G06G7/60; G06F15/18; G06N3/06; G06N99/00; (IPC1-7): G06N1/00; G06G7/60
Other References:
【文献】International Joint Conference on Neural Networks 1989 vol.2 p▲II▼.213-▲II▼.217
【文献】Yasunaga,Moritohi et.al:“A WAFER SCALE INTEGRATION NEURAL NETWORK UTILIZING COMPLETELY DIGITAL CIRCUITS”
【文献】Yasunaga,Moritohi et.al:“A WAFER SCALE INTEGRATION NEURAL NETWORK UTILIZING COMPLETELY DIGITAL CIRCUITS”
Attorney, Agent or Firm:
Takashi Ogaki