Title:
【発明の名称】ニューラルネットワーク及びニューラルメモリ
Document Type and Number:
Japanese Patent JP2001502834
Kind Code:
A
Abstract:
A neural pattern matcher is made up of an array of first sum and threshold SAT1 devices 18 each of which receives a number of inputs and a threshold value, and fires a 1 output if the number of inputs exceeds the threshold value. The outputs of the array of the SAT1 devices may be considered as a 2D image or generic template against which new data supplied into the registers 26 making up a data plane 24 are correlated at a correlation plane 20 of EX-NOR gates 22. The outputs of the EX-NOR gates themselves may be summed and thresholded by a seconded sum and threshold device 28 to provide a neural output '1' or '0' indicating match or no match. The matcher may therefore behave as a neural auto-associative memory which continually adapts to the input data to recognize data of a particular specified class.
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Inventors:
King, Douglas, Beberley, Stevenson
Application Number:
JP53347599A
Publication Date:
February 27, 2001
Filing Date:
December 18, 1998
Export Citation:
Assignee:
British Aerospace Public Limited Company
International Classes:
G06N3/04; G06F7/02; G06K9/64; G06N3/06; G06N3/063; G06T5/20; H03M7/16; (IPC1-7): G06N3/04
Attorney, Agent or Firm:
Shigeru Yagita (2 outside)