Title:
【発明の名称】ニューロプロセッサ
Document Type and Number:
Japanese Patent JP3177996
Kind Code:
B2
Abstract:
PURPOSE:To improve the calculating speed for learning a neural network by dividing a weighting memory for synapse coupling into plural memories. CONSTITUTION:This neuro-processor is constituted of weighting memories A 3 and B 4 for synapse coupling respectively divided into plural pieces, the 1st switching circuit 31 which selects the outputs of the memories 3 and 4, weight modification circuit 2, and the 2nd switching circuit 32 which distributes the output of the circuit 2 to the memories 3 and 4. Since the weighting memory for synapse coupling of this processor is divided into the memory 3 connected by means of the circuit 31 and the other memory 4 connected by means of the circuit 32, both memories 3 and 4 can be accessed in parallel with each other and reading out and writing can be respectively performed on the memories at the same time. Therefore, the using efficiency of a computing element can be improved and the time required for making learning calculation can be reduced.
Inventors:
Atsuo Inoue
Youichi Tamura
Masayuki Morishita
Shinichi Katsu
Youichi Tamura
Masayuki Morishita
Shinichi Katsu
Application Number:
JP8390391A
Publication Date:
June 18, 2001
Filing Date:
April 16, 1991
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G06F15/18; G06G7/60; G06N3/04; G06N3/063; G06N99/00; (IPC1-7): G06N3/063
Domestic Patent References:
| JP4266127A | ||||
| JP3268080A |
Other References:
上村、佐藤、溝口、天満、「パタンマッチングプロセッサ プロトタイプの試作」、電子情報通信学会技術研究報告（ＩＥ９０−１７７）、ｐ．２５−ｐ．３２（１９９１．３）
Attorney, Agent or Firm:
Fumio Iwahashi (2 others)