Title:
【発明の名称】オフセット補正回路及び直流増幅回路
Document Type and Number:
Japanese Patent JP3381572
Kind Code:
B2
Abstract:
An offset correction circuit containing an integrator is provided between output of a first DC amplifier and input of a second DC amplifier, and the integrator corrects not only an offset error caused by an input signal in the first DC amplifier, but also an offset error caused by an input signal in the second DC amplifier. Thus, the effect of the offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal in the two DC amplifiers can be canceled.
Inventors:
Tatsuhiko Takatsu
Application Number:
JP25904597A
Publication Date:
March 04, 2003
Filing Date:
September 24, 1997
Export Citation:
Assignee:
Ando Electric Co., Ltd.
International Classes:
G06G7/12; H03F1/30; H03F3/34; (IPC1-7): H03F3/34; G06G7/12
Domestic Patent References:
| JP6102294A | ||||
| JP57200130A | ||||
| JP1303806A | ||||
| JP1160712U | ||||
| JP3711914B1 |
Attorney, Agent or Firm:
Hiroshi Arafune (1 person outside)