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Title:
ERROR MONITOR CIRCUIT
Document Type and Number:
Japanese Patent JPH0746226
Kind Code:
A
Abstract:

PURPOSE: To monitor the real error number of reproduced data to be sent to a carrier equipment by detecting an unmatched number of active and standby reception data inputted from a transmission section to a reception section and detecting a parity error after reception of transmission data with a parity added thereto.

CONSTITUTION: A transmission means 1 adds a radio block frame synchronizing signal and a parity bit respectively to active distribution data and standby distribution data generated by dividing received data into two and sends the data by two frequencies f1, f2 as active transmission data and standby transmission data. A deciding means 4 at a receiver side checks the presence of a parity error in the active reception data and the standby reception data and sends line information generating the parity error as result of a decision. On the other hand, an uninterruptible changeover means 3 eliminates the synchronizing signal and the parity bit from the active reception data and the standby reception data and sends the result to the carrier equipment and the active data and the standby distribution data are compared one by one bit each at a comparison counter section 5 to detect unmatch. A data error sent from the means 4 and the section 5 is displayed on an error number display section 6.


Inventors:
OIDE KENICHI
Application Number:
JP19149693A
Publication Date:
February 14, 1995
Filing Date:
August 03, 1993
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04L1/00; H04L1/22; (IPC1-7): H04L1/00; H04L1/22
Attorney, Agent or Firm:
Teiichi



 
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