Title:
【発明の名称】レジスティブメモリ・エレメント
Document Type and Number:
Japanese Patent JP3256233
Kind Code:
B2
Abstract:
PCT No. PCT/GB92/01929 Sec. 371 Date Sep. 19, 1994 Sec. 102(e) Date Sep. 19, 1994 PCT Filed Oct. 20, 1992 PCT Pub. No. WO93/08575 PCT Pub. Date Apr. 29, 1993The resistance of a resistive memory element, e.g. a synaptic element is programmed, e.g. adjusted to a target value, by pulses of a constant height and variable width. One polarity gives an increase in resistance; the other polarity gives a decrease. A short pulse applied after a longer pulse appears to have no effect. After each polarity change short pulses can again be used to make small adjustments. In a preferred embodiment longer and longer pulses are used until the resistance overshoots the target value. After overshooting the polarity is reversed and a second series of pulses is used to obtain a closer approach to the target. The resistive element comprises a resistive layer located between two electrodes, e.g. a matrix of amorphous silicon doped with boron containing V. One electrode is Cr and the other is V.
Inventors:
Lecomber, Peter George
Rose, Marvin John
Hagit, Janos
Owen, Alan Ernest
Osborne, Ian Stuart
Snell, Anthony James
Rose, Marvin John
Hagit, Janos
Owen, Alan Ernest
Osborne, Ian Stuart
Snell, Anthony James
Application Number:
JP50756293A
Publication Date:
February 12, 2002
Filing Date:
October 20, 1992
Export Citation:
Assignee:
British Telecommunications Public Limited Company
International Classes:
G06G7/60; G06N3/063; G11C27/00; (IPC1-7): G06G7/60
Other References:
ＥＬＥＣＴＲＯＮＩＣＳ ＬＥＴＴＥＲＳ．ｖｏｌ．２４，ｎｏ．１９，１５ Ｓｅｐｔｅｍｂｅｒ １９８８，ＥＮＡＧＥ ＧＢ ｐｐ．１２３１−１２３２
Attorney, Agent or Firm:
Takehiko Suzue (3 outside)