Title:
【発明の名称】半導体集積回路
Document Type and Number:
Japanese Patent JP2861763
Kind Code:
B2
Abstract:
PURPOSE:To keep a power supply voltage margin and an external noise margin of a semiconductor integrated circuit including a master slave flip-flop of series gate configuration having a scan path function and to reduce the power consumption. CONSTITUTION:This integrated circuit is provided with at least plural buffer gates 105 receiving an internal scan path signal 1008 and a clock signal 103 and outputting a logic signal 1010 corresponding to a normal operating state and a scan path operating state of a master slave flip-flop 106, plural buffer gates 104 receiving a scan path signal 1007 and the clock signal 103 and outputting a logic signal 1009 corresponding to a normal operating state and a scan path operating state of the master slave flip-flop 106, and plural clock drivers 102 receiving a clock signal 1002 and outputting clock signals 1004, 1005.
Inventors:
KATAGIRI MASARU
Application Number:
JP30137493A
Publication Date:
February 24, 1999
Filing Date:
December 01, 1993
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G01R31/28; H03K3/289; H03K3/286; (IPC1-7): H03K3/286; G01R31/28; H03K3/289
Domestic Patent References:
| JP6218818A | ||||
| JP2141120A | ||||
| JP2152316A | ||||
| JP1263739A | ||||
| JP62143513A | ||||
| JP63222275A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)